Lectures
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Topic
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Reading
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Lecture
#1 |
Introduction: General Overview
of the Internet Architecture and Protocols |
What is the
Internet (And What makes it Run) Optical
Internet Architecture I |
Lecture
#2 |
Introduction to Internet
Routers and Packet Switches |
N. McKeown, M. Izzard, A. Mekkittikul,
W. Ellersick and M. Horowitz, The Tiny Tera: A
Packet Switch Core , Proc. Hot Interconnects V, Stanford University, August 1996. Nick
Mckeown, "Fast Switched
Backplane for a Gigabit Switched Router," Cisco White Paper. S. Keshav and R. Sharma, Issues
and Trends in Router Design, IEEE Communications Magazine, Vol. 36, No.
5, May 1998, pp. 144-151. "Routers
with a Single Stage of Buffering," "Analysis
of the Parallel Packet Switch Architecture," Lin,
B.; Keslassy, I., "The
Concurrent Matching Switch Architecture," IEEE/ACM Transactions on
Networking, vol.18, no.4, pp.1330-1343, Aug. 2010. |
Lecture
#3 |
Scheduling and Arbitration in
High-Speed Switches and Routers |
N. Mckeown, iSLIP:
A Scheduling Algorithm for Input-Queued Switches, IEEE Transactions on
Networking, Vol 7, No.2, April 1999. Y.
Jiang and M. Hamdi, "A fully
desynchronized round-robin matching scheduler for a VOQ packet switch architecture,"
2001 IEEE Workshop on High Performance Switching and Routing
, 2001, Page(s): 407 -411. Paolo
Giaccone, Balaji Prabhakar, Devavrat Shah, Towards
Simple, High-Performance Schedulers for High-Aggregate Bandwidth Switches,
IEEE INFOCOM 2002, New York, USA, June 2002. Paolo
Giaccone, Devavrat Shah, Balaji Prabhakar, An Implementable
Parallel Scheduler for Input-Queued Switches, Hot Interconnects 9,
Stanford, CA, USA, August 2001. D. Serpanos and P. Antoniadis, "FIRM:
A Class of Distributed Scheduling Algorithms for High-Speed ATM Switches with
Multiple Input Queues,” IEEE INFOCOM 2000. T.
Anderson, S. Owicki, J. Saxe, and C. Thacker,
"High-speed
switch scheduling for local-area networks," ACM TOCS, Nov. 1994,
Pages: 319 - 352. Yanming Shen, Panwar, S.S.; Chao, H.J.,
"SQUID:
A Practical 100% Throughput Scheduler for Crosspoint Buffered Switches,"
IEEE/ACM Transactions on Networking, vol.18, no.4, pp.1119-1131, Aug. 2010. |
Lecture #4 |
Introduction to Network-on-Chip
(NOC) |
Æthereal
Network on Chip: Concepts, Architectures, and Implementations, Kees Goossens , John Dielissen , Andrei Radulescu, IEEE Design & Test, v.22 n.5, p.414-421,
September 2005. A
survey of research and practices of Network-on-chip, Tobias Bjerregaard, Shankar Mahadevan,
ACM Computing Surveys,Volume
38 , Issue 1 (2006) Network
on chip: An architecture for billion transistor era.
A. Hemani, A. Jantsch,
S. Kumar, A. Postula, J. Öberg, M. Millberg, and
D. Lindqvist. In Proceeding of the IEEE NorChip Conference, November 2000. Route
packets, not wires: on-chip inteconnection networks, William J.
Dally, Brian Towles, Annual ACM IEEE Design Automation
Conference, Proceedings of the 38th annual Design Automation Conference. Basic
Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication
and Computation Orthogonalization, A. Ben Abdallah,
and M. Sowa, Symposium on Society, Science and Technology (TJASSST), Dec.
4-9th, 2006. Deadlock
free routing algorithms for mesh topology NoC systems with regions, R. Holsmark, M. Palesi, and
S. Kumar. In Proc. 9th EUROMICRO Conference on Digital System
Design, Architectures, Methods and Tools (DSD), September 2006. Palesi,
M.; Holsmark, R.; Kumar, S.; Catania, V. "Application
Specific Routing Algorithms for Networks on Chip," IEEE Transactions
on Parallel and Distributed Systems, vol.20, no.3, pp.316-330, March 2009. |
Lecture #5 |
Network-on-Chip Architectures
and Building Blocks |
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Lecture #6 & #7
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Lecture #8 |
Quality of Service in
Wireless LAN |
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Lecture #9 |
Quality-of-Service (QoS)
Provision in the Internet |
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Lecture #10 |
Switching Architectures for Optical Networks |
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